commit 51248398ce7eec538b4082a1cccea9acb9aede8a Author: Randy Jordan Date: Tue Jun 16 20:36:49 2026 -0500 Initial commit diff --git a/LICENSE.md b/LICENSE.md new file mode 100644 index 0000000..074265c --- /dev/null +++ b/LICENSE.md @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) [2026] [Randy Jordan] + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/README.md b/README.md new file mode 100644 index 0000000..7dc32d8 --- /dev/null +++ b/README.md @@ -0,0 +1,45 @@ +# kicad-template + +## Description +Most basic kicad-template. Design for 3v/5v breadboard power-supply. + +## Table of Contents + +* [Folders](#folders) +* [Libraries](#libraries) +* [Todos](#todos) +* [Acknowledgments](#acknowledgments) +* [License](#license) + + +## Folders +Explanation of folder structure. + +* Project + * cad `computer aided drawings and models for assembly / presentation.` + * cam `computer aided manufacturing drawings (gerbers). ` + * img `reference images for presentation / repo.` + * meta `meta-data for kicad template` + * lib `project local libraries for footprints, symbols, and models.` + * ref `reference calculations and datasheets` + * templates `project local file templates` + +## Libraries +These libraries and plugins are useful.
+## Todos + +## Acknowledgments + +[nguyen-v KDT Hierarchical KiBot](https://github.com/nguyen-v/KDT_Hierarchical_KiBot) +[Tom Preston-Werner README Driven Development](https://tom.preston-werner.com/2010/08/23/readme-driven-development)
+[Make a README](https://www.makeareadme.com/)
+[Choose a LICENSE](https://choosealicense.com/)
+[Gitignore Templates](https://github.com/github/gitignore)
+[PCB Design Rule Check](https://www.pcbway.com/pcb_prototype/PCB_Design_Rule_Check.html) +[PCB Design Rules](https://github.com/pcbway/PCBWay-Design-Rules)
+ + +## License + +This project is licensed under the MIT License - see the [MIT License](LICENSE.md) file for details. + diff --git a/cad/.gitkeep b/cad/.gitkeep new file mode 100644 index 0000000..e69de29 diff --git a/cam/.gitkeep b/cam/.gitkeep new file mode 100644 index 0000000..e69de29 diff --git a/cam/gerbers/.gitkeep b/cam/gerbers/.gitkeep new file mode 100644 index 0000000..e69de29 diff --git a/kicad_template.kicad_dru b/kicad_template.kicad_dru new file mode 100644 index 0000000..94378fc --- /dev/null +++ b/kicad_template.kicad_dru @@ -0,0 +1,169 @@ +(version 1) +#PCBWay Custom DRC for Kicad 7 + +# ----------------------------------- Minimum trace width and spacing (PICK ONE) -------------------- + +# 2oz copper +#(rule "Minimum Trace Width and Spacing (outer layer)" +#(constraint track_width (min 0.1524mm)) +#(constraint clearance (min 0.1778mm)) +#(layer outer) +#(condition "A.Type == 'track'")) + +#(rule "Minimum Trace Width and Spacing (innner layer)" +#(constraint track_width (min 0.1524mm)) +#(constraint clearance (min 0.1778mm)) +#(layer inner) +#(condition "A.Type == 'track'")) + + +# 2-layer, 1oz copper +(rule "Minimum Trace Width and Spacing (outer layer)" +(constraint track_width (min 0.127mm)) +(constraint clearance (min 0.127mm)) +(layer outer) +(condition "A.Type == 'track'")) + +(rule "Minimum Trace Width and Spacing (inner layer)" +(constraint track_width (min 0.1mm)) +(constraint clearance (min 0.1mm)) +(layer inner) +(condition "A.Type == 'track'")) + +# 4-layer , 1oz and 0.5oz copper +#(rule "Minimum Trace Width and Spacing (outer layer)" +#(constraint track_width (min 0.09mm)) +#(constraint clearance (min 0.09mm)) +#(layer outer) +#(condition "A.Type == 'track'")) + +#(rule "Minimum Trace Width and Spacing (inner layer)" +#(constraint track_width (min 0.1mm)) +#(constraint clearance (min 0.09mm)) +#(layer inner) +#(condition "A.Type == 'track'")) + +# ------------------------------------------------------------------------------------------------------ + +# Drill/hole size - listed here to maintain order of rule application. Must not override rule set in Via hole/diameter size below. +(rule "drill hole size (mechanical)" +(constraint hole_size (min 0.15mm) (max 6.3mm))) + +# ----------------------------------- Via hole/diameter size (PICK ONE) ------------------------------------ + +# 2-layer standard +(rule "Minimum Via Diameter and Hole Size" +(constraint hole_size (min 0.3mm)) +(constraint via_diameter (min 0.5mm)) +(condition "A.Type == 'via'")) + +# 4-layer standard +#(rule "Minimum Via Diameter and Hole Size" +#(constraint hole_size (min 0.3mm)) +#(constraint via_diameter (min 0.45mm)) +#(condition "A.Type == 'via'")) + +# 4-layer advanced +#(rule "Minimum Via Diameter and Hole Size" +#(constraint hole_size (min 0.25mm)) +#(constraint via_diameter (min 0.4mm)) +#(constraint disallow buried_via) +#(condition "A.Type == 'via'")) + +# 4-layer advanced +#(rule "Minimum Via Diameter and Hole Size" +#(constraint hole_size (min 0.2mm)) +#(constraint via_diameter (min 0.35mm)) +#(condition "A.Type == 'via'")) + +# 4-layer advanced +#(rule "Minimum Via Diameter and Hole Size" +#(constraint hole_size (min 0.15mm)) +#(constraint via_diameter (min 0.3mm)) +#(condition "A.Type == 'via'")) + +# ----------------------------------- Drill/hole size ------------------------------------ + +(rule "PTH Hole Size" +(constraint hole_size (min 0.2mm) (max 6.35mm)) +(condition "A.Type != 'Via' && A.isPlated()")) + +(rule "Minimum Non-plated Hole Size" +(constraint hole_size (min 0.5mm)) +(condition "A.Type == 'pad' && !A.isPlated()")) + +(rule "Pad Size" +(constraint hole_size (min 0.5mm)) +(constraint annular_width (min 0.25mm)) +(condition "A.Type == 'Pad' && A.isPlated()")) + +(rule "Minimum Castellated Hole Size" +(constraint hole_size (min 0.6mm)) +(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")) + +(rule "Min. Plated Slot Width" +(constraint hole_size (min 0.5mm)) +(condition "(A.Hole_Size_X != A.Hole_Size_Y) && A.isPlated()")) + +(rule "Min. Non-Plated Slot Width" +(constraint hole_size (min 0.8mm)) +(condition "(A.Hole_Size_X != A.Hole_Size_Y) && !A.isPlated()")) + +# ----------------------------------- Minimum clearance ---------------------------------- +(rule "hole to hole clearance (different nets)" +(constraint hole_to_hole (min 0.5mm)) +(condition "A.Net != B.Net")) + +(rule "via to track clearance" +(constraint hole_clearance (min 0.254mm)) +(condition "A.Type == 'via' && B.Type == 'track'")) + +(rule "via to via clearance (same nets)" +(constraint hole_to_hole (min 0.254mm)) +(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net")) + +(rule "pad to pad clearance (with hole, different nets)" +(constraint hole_to_hole (min 0.5mm)) +(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net")) + +(rule "pad to pad clearance (without hole, different nets)" +(constraint clearance (min 0.127mm)) +(condition "A.Type == 'Pad' && B.Type == 'Pad'")) + +(rule "NPTH to Track clearance" +(constraint hole_clearance (min 0.254mm)) +(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'")) + +(rule "NPTH with copper around" +(constraint hole_clearance (min 0.20mm)) +(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type != 'track'")) + +(rule "PTH to Track clearance" +(constraint hole_clearance (min 0.33mm)) +(condition "A.isPlated() && A.Type != 'Via' && B.Type == 'track'")) + +(rule "Pad to Track clearance" +(constraint clearance (min 0.2mm)) +(condition "A.isPlated() && A.Type != 'Via' && B.Type == 'track'")) + +# ----------------------------------- Board Outlines (PICK ONE) ------------------------------------- +#Default Routed Edge Clearance +(rule "Trace to Outline" +(constraint edge_clearance (min 0.3mm)) +(condition "A.Type == 'track'")) + +#Special Clearance for V-Score Edges +#(rule "Trace to V-Cut" +#(constraint edge_clearance (min 0.4mm)) +#(condition "A.Type == 'track'")) + +# ----------------------------------- silkscreen -------------------------- +(rule "Minimum Text" +(constraint text_thickness (min 0.15mm)) +(constraint text_height (min 0.8mm)) +(layer "?.Silkscreen")) + +(rule "Pad to Silkscreen" +(constraint silk_clearance (min 0.15mm)) +(layer outer) +(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')")) diff --git a/kicad_template.kicad_pcb b/kicad_template.kicad_pcb new file mode 100644 index 0000000..c547853 --- /dev/null +++ b/kicad_template.kicad_pcb @@ -0,0 +1,2 @@ +(kicad_pcb (version 20241229) (generator "pcbnew") (generator_version "9.0") +) \ No newline at end of file diff --git a/kicad_template.kicad_pro b/kicad_template.kicad_pro new file mode 100644 index 0000000..a6ad604 --- /dev/null +++ b/kicad_template.kicad_pro @@ -0,0 +1,83 @@ +{ + "board": { + "3dviewports": [], + "design_settings": { + "defaults": {}, + "diff_pair_dimensions": [], + "drc_exclusions": [], + "rules": {}, + "track_widths": [], + "via_dimensions": [] + }, + "ipc2581": { + "dist": "", + "distpn": "", + "internal_id": "", + "mfg": "", + "mpn": "" + }, + "layer_pairs": [], + "layer_presets": [], + "viewports": [] + }, + "boards": [], + "cvpcb": { + "equivalence_files": [] + }, + "libraries": { + "pinned_footprint_libs": [], + "pinned_symbol_libs": [] + }, + "meta": { + "filename": "kicad_template.kicad_pro", + "version": 3 + }, + "net_settings": { + "classes": [ + { + "bus_width": 12, + "clearance": 0.2, + "diff_pair_gap": 0.25, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.2, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "Default", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2147483647, + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.2, + "via_diameter": 0.6, + "via_drill": 0.3, + "wire_width": 6 + } + ], + "meta": { + "version": 4 + }, + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [] + }, + "pcbnew": { + "last_paths": { + "gencad": "", + "idf": "", + "netlist": "", + "plot": "", + "pos_files": "", + "specctra_dsn": "", + "step": "", + "svg": "", + "vrml": "" + }, + "page_layout_descr_file": "" + }, + "schematic": { + "legacy_lib_dir": "", + "legacy_lib_list": [] + }, + "sheets": [], + "text_variables": {} +} diff --git a/kicad_template.kicad_sch b/kicad_template.kicad_sch new file mode 100644 index 0000000..4a27fb9 --- /dev/null +++ b/kicad_template.kicad_sch @@ -0,0 +1,14 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid 8ac7f1f9-c31f-47fb-af67-a350a1922114) + (paper "A4") + (lib_symbols) + (sheet_instances + (path "/" + (page "1") + ) + ) + (embedded_fonts no) +) \ No newline at end of file diff --git a/lib/.gitkeep b/lib/.gitkeep new file mode 100644 index 0000000..e69de29 diff --git a/meta/icon.png b/meta/icon.png new file mode 100644 index 0000000..626891b Binary files /dev/null and b/meta/icon.png differ diff --git a/meta/info.html b/meta/info.html new file mode 100644 index 0000000..0c6607d --- /dev/null +++ b/meta/info.html @@ -0,0 +1,12 @@ + + + + + Randy Jordan - KiCAD Design Template (Hierarchical) + + +

Randy Jordan - KiCAD Design Template (Hierarchical)

+

This creates a project with predefined design rules for PCBWay.

+ + + diff --git a/ref/evvosemi_5272_AMS1117-5.0.pdf b/ref/evvosemi_5272_AMS1117-5.0.pdf new file mode 100644 index 0000000..0088efc Binary files /dev/null and b/ref/evvosemi_5272_AMS1117-5.0.pdf differ diff --git a/ref/umw_ams_1117_voltage_regulator.pdf b/ref/umw_ams_1117_voltage_regulator.pdf new file mode 100644 index 0000000..e3d6b2c Binary files /dev/null and b/ref/umw_ams_1117_voltage_regulator.pdf differ diff --git a/templates/KiCAD_Custom_DRC_Rules_for_PCBWay.kicad_dru b/templates/KiCAD_Custom_DRC_Rules_for_PCBWay.kicad_dru new file mode 100644 index 0000000..94378fc --- /dev/null +++ b/templates/KiCAD_Custom_DRC_Rules_for_PCBWay.kicad_dru @@ -0,0 +1,169 @@ +(version 1) +#PCBWay Custom DRC for Kicad 7 + +# ----------------------------------- Minimum trace width and spacing (PICK ONE) -------------------- + +# 2oz copper +#(rule "Minimum Trace Width and Spacing (outer layer)" +#(constraint track_width (min 0.1524mm)) +#(constraint clearance (min 0.1778mm)) +#(layer outer) +#(condition "A.Type == 'track'")) + +#(rule "Minimum Trace Width and Spacing (innner layer)" +#(constraint track_width (min 0.1524mm)) +#(constraint clearance (min 0.1778mm)) +#(layer inner) +#(condition "A.Type == 'track'")) + + +# 2-layer, 1oz copper +(rule "Minimum Trace Width and Spacing (outer layer)" +(constraint track_width (min 0.127mm)) +(constraint clearance (min 0.127mm)) +(layer outer) +(condition "A.Type == 'track'")) + +(rule "Minimum Trace Width and Spacing (inner layer)" +(constraint track_width (min 0.1mm)) +(constraint clearance (min 0.1mm)) +(layer inner) +(condition "A.Type == 'track'")) + +# 4-layer , 1oz and 0.5oz copper +#(rule "Minimum Trace Width and Spacing (outer layer)" +#(constraint track_width (min 0.09mm)) +#(constraint clearance (min 0.09mm)) +#(layer outer) +#(condition "A.Type == 'track'")) + +#(rule "Minimum Trace Width and Spacing (inner layer)" +#(constraint track_width (min 0.1mm)) +#(constraint clearance (min 0.09mm)) +#(layer inner) +#(condition "A.Type == 'track'")) + +# ------------------------------------------------------------------------------------------------------ + +# Drill/hole size - listed here to maintain order of rule application. Must not override rule set in Via hole/diameter size below. +(rule "drill hole size (mechanical)" +(constraint hole_size (min 0.15mm) (max 6.3mm))) + +# ----------------------------------- Via hole/diameter size (PICK ONE) ------------------------------------ + +# 2-layer standard +(rule "Minimum Via Diameter and Hole Size" +(constraint hole_size (min 0.3mm)) +(constraint via_diameter (min 0.5mm)) +(condition "A.Type == 'via'")) + +# 4-layer standard +#(rule "Minimum Via Diameter and Hole Size" +#(constraint hole_size (min 0.3mm)) +#(constraint via_diameter (min 0.45mm)) +#(condition "A.Type == 'via'")) + +# 4-layer advanced +#(rule "Minimum Via Diameter and Hole Size" +#(constraint hole_size (min 0.25mm)) +#(constraint via_diameter (min 0.4mm)) +#(constraint disallow buried_via) +#(condition "A.Type == 'via'")) + +# 4-layer advanced +#(rule "Minimum Via Diameter and Hole Size" +#(constraint hole_size (min 0.2mm)) +#(constraint via_diameter (min 0.35mm)) +#(condition "A.Type == 'via'")) + +# 4-layer advanced +#(rule "Minimum Via Diameter and Hole Size" +#(constraint hole_size (min 0.15mm)) +#(constraint via_diameter (min 0.3mm)) +#(condition "A.Type == 'via'")) + +# ----------------------------------- Drill/hole size ------------------------------------ + +(rule "PTH Hole Size" +(constraint hole_size (min 0.2mm) (max 6.35mm)) +(condition "A.Type != 'Via' && A.isPlated()")) + +(rule "Minimum Non-plated Hole Size" +(constraint hole_size (min 0.5mm)) +(condition "A.Type == 'pad' && !A.isPlated()")) + +(rule "Pad Size" +(constraint hole_size (min 0.5mm)) +(constraint annular_width (min 0.25mm)) +(condition "A.Type == 'Pad' && A.isPlated()")) + +(rule "Minimum Castellated Hole Size" +(constraint hole_size (min 0.6mm)) +(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")) + +(rule "Min. Plated Slot Width" +(constraint hole_size (min 0.5mm)) +(condition "(A.Hole_Size_X != A.Hole_Size_Y) && A.isPlated()")) + +(rule "Min. Non-Plated Slot Width" +(constraint hole_size (min 0.8mm)) +(condition "(A.Hole_Size_X != A.Hole_Size_Y) && !A.isPlated()")) + +# ----------------------------------- Minimum clearance ---------------------------------- +(rule "hole to hole clearance (different nets)" +(constraint hole_to_hole (min 0.5mm)) +(condition "A.Net != B.Net")) + +(rule "via to track clearance" +(constraint hole_clearance (min 0.254mm)) +(condition "A.Type == 'via' && B.Type == 'track'")) + +(rule "via to via clearance (same nets)" +(constraint hole_to_hole (min 0.254mm)) +(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net")) + +(rule "pad to pad clearance (with hole, different nets)" +(constraint hole_to_hole (min 0.5mm)) +(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net")) + +(rule "pad to pad clearance (without hole, different nets)" +(constraint clearance (min 0.127mm)) +(condition "A.Type == 'Pad' && B.Type == 'Pad'")) + +(rule "NPTH to Track clearance" +(constraint hole_clearance (min 0.254mm)) +(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'")) + +(rule "NPTH with copper around" +(constraint hole_clearance (min 0.20mm)) +(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type != 'track'")) + +(rule "PTH to Track clearance" +(constraint hole_clearance (min 0.33mm)) +(condition "A.isPlated() && A.Type != 'Via' && B.Type == 'track'")) + +(rule "Pad to Track clearance" +(constraint clearance (min 0.2mm)) +(condition "A.isPlated() && A.Type != 'Via' && B.Type == 'track'")) + +# ----------------------------------- Board Outlines (PICK ONE) ------------------------------------- +#Default Routed Edge Clearance +(rule "Trace to Outline" +(constraint edge_clearance (min 0.3mm)) +(condition "A.Type == 'track'")) + +#Special Clearance for V-Score Edges +#(rule "Trace to V-Cut" +#(constraint edge_clearance (min 0.4mm)) +#(condition "A.Type == 'track'")) + +# ----------------------------------- silkscreen -------------------------- +(rule "Minimum Text" +(constraint text_thickness (min 0.15mm)) +(constraint text_height (min 0.8mm)) +(layer "?.Silkscreen")) + +(rule "Pad to Silkscreen" +(constraint silk_clearance (min 0.15mm)) +(layer outer) +(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')")) diff --git a/templates/fab_template.kicad_wks b/templates/fab_template.kicad_wks new file mode 100644 index 0000000..7355482 --- /dev/null +++ b/templates/fab_template.kicad_wks @@ -0,0 +1,553 @@ +(kicad_wks + (version 20231118) + (generator "pl_editor") + (generator_version "8.0") + (setup + (textsize 1.5 1.5) + (linewidth 0.15) + (textlinewidth 0.15) + (left_margin 10) + (right_margin 10) + (top_margin 10) + (bottom_margin 10) + ) + (rect + (name "") + (start 0 0 ltcorner) + (end 0 0) + (repeat 2) + (incrx 2) + (incry 2) + ) + (line + (name "") + (start 50 2 ltcorner) + (end 50 0 ltcorner) + (repeat 30) + (incrx 50) + ) + (tbtext "1" + (name "") + (pos 25 1 ltcorner) + (font + (size 1.3 1.3) + ) + (repeat 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