Initial commit
This commit is contained in:
+21
@@ -0,0 +1,21 @@
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||||
MIT License
|
||||
|
||||
Copyright (c) [2026] [Randy Jordan]
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||||
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Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
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||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
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@@ -0,0 +1,45 @@
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# kicad-template
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## Description
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Most basic kicad-template. Design for 3v/5v breadboard power-supply.
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## Table of Contents
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* [Folders](#folders)
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* [Libraries](#libraries)
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* [Todos](#todos)
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* [Acknowledgments](#acknowledgments)
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* [License](#license)
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## Folders
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Explanation of folder structure.
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* Project
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* cad `computer aided drawings and models for assembly / presentation.`
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* cam `computer aided manufacturing drawings (gerbers). `
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* img `reference images for presentation / repo.`
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* meta `meta-data for kicad template`
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* lib `project local libraries for footprints, symbols, and models.`
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* ref `reference calculations and datasheets`
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* templates `project local file templates`
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## Libraries
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These libraries and plugins are useful. <br>
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## Todos
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## Acknowledgments
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[nguyen-v KDT Hierarchical KiBot](https://github.com/nguyen-v/KDT_Hierarchical_KiBot)
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[Tom Preston-Werner README Driven Development](https://tom.preston-werner.com/2010/08/23/readme-driven-development)<br>
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[Make a README](https://www.makeareadme.com/)<br>
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[Choose a LICENSE](https://choosealicense.com/)<br>
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[Gitignore Templates](https://github.com/github/gitignore)<br>
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[PCB Design Rule Check](https://www.pcbway.com/pcb_prototype/PCB_Design_Rule_Check.html)
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[PCB Design Rules](https://github.com/pcbway/PCBWay-Design-Rules)<br>
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## License
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This project is licensed under the MIT License - see the [MIT License](LICENSE.md) file for details.
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@@ -0,0 +1,169 @@
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(version 1)
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#PCBWay Custom DRC for Kicad 7
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# ----------------------------------- Minimum trace width and spacing (PICK ONE) --------------------
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# 2oz copper
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#(rule "Minimum Trace Width and Spacing (outer layer)"
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#(constraint track_width (min 0.1524mm))
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#(constraint clearance (min 0.1778mm))
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#(layer outer)
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#(condition "A.Type == 'track'"))
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#(rule "Minimum Trace Width and Spacing (innner layer)"
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#(constraint track_width (min 0.1524mm))
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#(constraint clearance (min 0.1778mm))
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#(layer inner)
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#(condition "A.Type == 'track'"))
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# 2-layer, 1oz copper
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(rule "Minimum Trace Width and Spacing (outer layer)"
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(constraint track_width (min 0.127mm))
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(constraint clearance (min 0.127mm))
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(layer outer)
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(condition "A.Type == 'track'"))
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(rule "Minimum Trace Width and Spacing (inner layer)"
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(constraint track_width (min 0.1mm))
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(constraint clearance (min 0.1mm))
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(layer inner)
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(condition "A.Type == 'track'"))
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# 4-layer , 1oz and 0.5oz copper
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#(rule "Minimum Trace Width and Spacing (outer layer)"
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#(constraint track_width (min 0.09mm))
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#(constraint clearance (min 0.09mm))
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#(layer outer)
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#(condition "A.Type == 'track'"))
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#(rule "Minimum Trace Width and Spacing (inner layer)"
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#(constraint track_width (min 0.1mm))
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#(constraint clearance (min 0.09mm))
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#(layer inner)
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#(condition "A.Type == 'track'"))
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# ------------------------------------------------------------------------------------------------------
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|
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# Drill/hole size - listed here to maintain order of rule application. Must not override rule set in Via hole/diameter size below.
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(rule "drill hole size (mechanical)"
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(constraint hole_size (min 0.15mm) (max 6.3mm)))
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|
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# ----------------------------------- Via hole/diameter size (PICK ONE) ------------------------------------
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|
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# 2-layer standard
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(rule "Minimum Via Diameter and Hole Size"
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(constraint hole_size (min 0.3mm))
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(constraint via_diameter (min 0.5mm))
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(condition "A.Type == 'via'"))
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|
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# 4-layer standard
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#(rule "Minimum Via Diameter and Hole Size"
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||||
#(constraint hole_size (min 0.3mm))
|
||||
#(constraint via_diameter (min 0.45mm))
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||||
#(condition "A.Type == 'via'"))
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||||
|
||||
# 4-layer advanced
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||||
#(rule "Minimum Via Diameter and Hole Size"
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#(constraint hole_size (min 0.25mm))
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#(constraint via_diameter (min 0.4mm))
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#(constraint disallow buried_via)
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||||
#(condition "A.Type == 'via'"))
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||||
|
||||
# 4-layer advanced
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||||
#(rule "Minimum Via Diameter and Hole Size"
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||||
#(constraint hole_size (min 0.2mm))
|
||||
#(constraint via_diameter (min 0.35mm))
|
||||
#(condition "A.Type == 'via'"))
|
||||
|
||||
# 4-layer advanced
|
||||
#(rule "Minimum Via Diameter and Hole Size"
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||||
#(constraint hole_size (min 0.15mm))
|
||||
#(constraint via_diameter (min 0.3mm))
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#(condition "A.Type == 'via'"))
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||||
|
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# ----------------------------------- Drill/hole size ------------------------------------
|
||||
|
||||
(rule "PTH Hole Size"
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(constraint hole_size (min 0.2mm) (max 6.35mm))
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(condition "A.Type != 'Via' && A.isPlated()"))
|
||||
|
||||
(rule "Minimum Non-plated Hole Size"
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||||
(constraint hole_size (min 0.5mm))
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(condition "A.Type == 'pad' && !A.isPlated()"))
|
||||
|
||||
(rule "Pad Size"
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||||
(constraint hole_size (min 0.5mm))
|
||||
(constraint annular_width (min 0.25mm))
|
||||
(condition "A.Type == 'Pad' && A.isPlated()"))
|
||||
|
||||
(rule "Minimum Castellated Hole Size"
|
||||
(constraint hole_size (min 0.6mm))
|
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(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))
|
||||
|
||||
(rule "Min. Plated Slot Width"
|
||||
(constraint hole_size (min 0.5mm))
|
||||
(condition "(A.Hole_Size_X != A.Hole_Size_Y) && A.isPlated()"))
|
||||
|
||||
(rule "Min. Non-Plated Slot Width"
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||||
(constraint hole_size (min 0.8mm))
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||||
(condition "(A.Hole_Size_X != A.Hole_Size_Y) && !A.isPlated()"))
|
||||
|
||||
# ----------------------------------- Minimum clearance ----------------------------------
|
||||
(rule "hole to hole clearance (different nets)"
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||||
(constraint hole_to_hole (min 0.5mm))
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(condition "A.Net != B.Net"))
|
||||
|
||||
(rule "via to track clearance"
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||||
(constraint hole_clearance (min 0.254mm))
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(condition "A.Type == 'via' && B.Type == 'track'"))
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||||
|
||||
(rule "via to via clearance (same nets)"
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(constraint hole_to_hole (min 0.254mm))
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(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))
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||||
|
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(rule "pad to pad clearance (with hole, different nets)"
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(constraint hole_to_hole (min 0.5mm))
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(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
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|
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(rule "pad to pad clearance (without hole, different nets)"
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||||
(constraint clearance (min 0.127mm))
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||||
(condition "A.Type == 'Pad' && B.Type == 'Pad'"))
|
||||
|
||||
(rule "NPTH to Track clearance"
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||||
(constraint hole_clearance (min 0.254mm))
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(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))
|
||||
|
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(rule "NPTH with copper around"
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(constraint hole_clearance (min 0.20mm))
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(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type != 'track'"))
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||||
|
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(rule "PTH to Track clearance"
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(constraint hole_clearance (min 0.33mm))
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||||
(condition "A.isPlated() && A.Type != 'Via' && B.Type == 'track'"))
|
||||
|
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(rule "Pad to Track clearance"
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(constraint clearance (min 0.2mm))
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(condition "A.isPlated() && A.Type != 'Via' && B.Type == 'track'"))
|
||||
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# ----------------------------------- Board Outlines (PICK ONE) -------------------------------------
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#Default Routed Edge Clearance
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||||
(rule "Trace to Outline"
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||||
(constraint edge_clearance (min 0.3mm))
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(condition "A.Type == 'track'"))
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#Special Clearance for V-Score Edges
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||||
#(rule "Trace to V-Cut"
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||||
#(constraint edge_clearance (min 0.4mm))
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||||
#(condition "A.Type == 'track'"))
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||||
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# ----------------------------------- silkscreen --------------------------
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||||
(rule "Minimum Text"
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||||
(constraint text_thickness (min 0.15mm))
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||||
(constraint text_height (min 0.8mm))
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||||
(layer "?.Silkscreen"))
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||||
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(rule "Pad to Silkscreen"
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||||
(constraint silk_clearance (min 0.15mm))
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(layer outer)
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||||
(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))
|
||||
@@ -0,0 +1,2 @@
|
||||
(kicad_pcb (version 20241229) (generator "pcbnew") (generator_version "9.0")
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||||
)
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||||
@@ -0,0 +1,83 @@
|
||||
{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"design_settings": {
|
||||
"defaults": {},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"rules": {},
|
||||
"track_widths": [],
|
||||
"via_dimensions": []
|
||||
},
|
||||
"ipc2581": {
|
||||
"dist": "",
|
||||
"distpn": "",
|
||||
"internal_id": "",
|
||||
"mfg": "",
|
||||
"mpn": ""
|
||||
},
|
||||
"layer_pairs": [],
|
||||
"layer_presets": [],
|
||||
"viewports": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "kicad_template.kicad_pro",
|
||||
"version": 3
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 2147483647,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.2,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 4
|
||||
},
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": []
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"plot": "",
|
||||
"pos_files": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"svg": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": []
|
||||
},
|
||||
"sheets": [],
|
||||
"text_variables": {}
|
||||
}
|
||||
@@ -0,0 +1,14 @@
|
||||
(kicad_sch
|
||||
(version 20250114)
|
||||
(generator "eeschema")
|
||||
(generator_version "9.0")
|
||||
(uuid 8ac7f1f9-c31f-47fb-af67-a350a1922114)
|
||||
(paper "A4")
|
||||
(lib_symbols)
|
||||
(sheet_instances
|
||||
(path "/"
|
||||
(page "1")
|
||||
)
|
||||
)
|
||||
(embedded_fonts no)
|
||||
)
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 4.4 KiB |
@@ -0,0 +1,12 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
<html>
|
||||
<head>
|
||||
<meta HTTP-EQUIV="CONTENT-TYPE" CONTENT="text/html; charset=utf-8">
|
||||
<title>Randy Jordan - KiCAD Design Template (Hierarchical)</title>
|
||||
</head>
|
||||
<body>
|
||||
<h2>Randy Jordan - KiCAD Design Template (Hierarchical)</h2>
|
||||
<p> This creates a project with predefined design rules for PCBWay.</p>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,169 @@
|
||||
(version 1)
|
||||
#PCBWay Custom DRC for Kicad 7
|
||||
|
||||
# ----------------------------------- Minimum trace width and spacing (PICK ONE) --------------------
|
||||
|
||||
# 2oz copper
|
||||
#(rule "Minimum Trace Width and Spacing (outer layer)"
|
||||
#(constraint track_width (min 0.1524mm))
|
||||
#(constraint clearance (min 0.1778mm))
|
||||
#(layer outer)
|
||||
#(condition "A.Type == 'track'"))
|
||||
|
||||
#(rule "Minimum Trace Width and Spacing (innner layer)"
|
||||
#(constraint track_width (min 0.1524mm))
|
||||
#(constraint clearance (min 0.1778mm))
|
||||
#(layer inner)
|
||||
#(condition "A.Type == 'track'"))
|
||||
|
||||
|
||||
# 2-layer, 1oz copper
|
||||
(rule "Minimum Trace Width and Spacing (outer layer)"
|
||||
(constraint track_width (min 0.127mm))
|
||||
(constraint clearance (min 0.127mm))
|
||||
(layer outer)
|
||||
(condition "A.Type == 'track'"))
|
||||
|
||||
(rule "Minimum Trace Width and Spacing (inner layer)"
|
||||
(constraint track_width (min 0.1mm))
|
||||
(constraint clearance (min 0.1mm))
|
||||
(layer inner)
|
||||
(condition "A.Type == 'track'"))
|
||||
|
||||
# 4-layer , 1oz and 0.5oz copper
|
||||
#(rule "Minimum Trace Width and Spacing (outer layer)"
|
||||
#(constraint track_width (min 0.09mm))
|
||||
#(constraint clearance (min 0.09mm))
|
||||
#(layer outer)
|
||||
#(condition "A.Type == 'track'"))
|
||||
|
||||
#(rule "Minimum Trace Width and Spacing (inner layer)"
|
||||
#(constraint track_width (min 0.1mm))
|
||||
#(constraint clearance (min 0.09mm))
|
||||
#(layer inner)
|
||||
#(condition "A.Type == 'track'"))
|
||||
|
||||
# ------------------------------------------------------------------------------------------------------
|
||||
|
||||
# Drill/hole size - listed here to maintain order of rule application. Must not override rule set in Via hole/diameter size below.
|
||||
(rule "drill hole size (mechanical)"
|
||||
(constraint hole_size (min 0.15mm) (max 6.3mm)))
|
||||
|
||||
# ----------------------------------- Via hole/diameter size (PICK ONE) ------------------------------------
|
||||
|
||||
# 2-layer standard
|
||||
(rule "Minimum Via Diameter and Hole Size"
|
||||
(constraint hole_size (min 0.3mm))
|
||||
(constraint via_diameter (min 0.5mm))
|
||||
(condition "A.Type == 'via'"))
|
||||
|
||||
# 4-layer standard
|
||||
#(rule "Minimum Via Diameter and Hole Size"
|
||||
#(constraint hole_size (min 0.3mm))
|
||||
#(constraint via_diameter (min 0.45mm))
|
||||
#(condition "A.Type == 'via'"))
|
||||
|
||||
# 4-layer advanced
|
||||
#(rule "Minimum Via Diameter and Hole Size"
|
||||
#(constraint hole_size (min 0.25mm))
|
||||
#(constraint via_diameter (min 0.4mm))
|
||||
#(constraint disallow buried_via)
|
||||
#(condition "A.Type == 'via'"))
|
||||
|
||||
# 4-layer advanced
|
||||
#(rule "Minimum Via Diameter and Hole Size"
|
||||
#(constraint hole_size (min 0.2mm))
|
||||
#(constraint via_diameter (min 0.35mm))
|
||||
#(condition "A.Type == 'via'"))
|
||||
|
||||
# 4-layer advanced
|
||||
#(rule "Minimum Via Diameter and Hole Size"
|
||||
#(constraint hole_size (min 0.15mm))
|
||||
#(constraint via_diameter (min 0.3mm))
|
||||
#(condition "A.Type == 'via'"))
|
||||
|
||||
# ----------------------------------- Drill/hole size ------------------------------------
|
||||
|
||||
(rule "PTH Hole Size"
|
||||
(constraint hole_size (min 0.2mm) (max 6.35mm))
|
||||
(condition "A.Type != 'Via' && A.isPlated()"))
|
||||
|
||||
(rule "Minimum Non-plated Hole Size"
|
||||
(constraint hole_size (min 0.5mm))
|
||||
(condition "A.Type == 'pad' && !A.isPlated()"))
|
||||
|
||||
(rule "Pad Size"
|
||||
(constraint hole_size (min 0.5mm))
|
||||
(constraint annular_width (min 0.25mm))
|
||||
(condition "A.Type == 'Pad' && A.isPlated()"))
|
||||
|
||||
(rule "Minimum Castellated Hole Size"
|
||||
(constraint hole_size (min 0.6mm))
|
||||
(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))
|
||||
|
||||
(rule "Min. Plated Slot Width"
|
||||
(constraint hole_size (min 0.5mm))
|
||||
(condition "(A.Hole_Size_X != A.Hole_Size_Y) && A.isPlated()"))
|
||||
|
||||
(rule "Min. Non-Plated Slot Width"
|
||||
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# ----------------------------------- Minimum clearance ----------------------------------
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(rule "via to via clearance (same nets)"
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(rule "pad to pad clearance (with hole, different nets)"
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|
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(rule "pad to pad clearance (without hole, different nets)"
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|
||||
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|
||||
|
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(rule "NPTH to Track clearance"
|
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|
||||
|
||||
(rule "NPTH with copper around"
|
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|
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|
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(rule "PTH to Track clearance"
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|
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(rule "Pad to Track clearance"
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|
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|
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# ----------------------------------- Board Outlines (PICK ONE) -------------------------------------
|
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#Default Routed Edge Clearance
|
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(rule "Trace to Outline"
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|
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#Special Clearance for V-Score Edges
|
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# ----------------------------------- silkscreen --------------------------
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(constraint text_height (min 0.8mm))
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(layer "?.Silkscreen"))
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(rule "Pad to Silkscreen"
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(layer outer)
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(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))
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Reference in New Issue
Block a user